The present invention relates to a method and/or architecture for frequency generation control generally and, more particularly, to a method and/or architecture for frequency generation control that minimizes power consumption.
Conventional frequency generators may use a large amount of current. For low power designs, current consumption of frequency generators can be a significant part of the operating current (ICC) and the stand-by current (ISB) of a device. It would be desirable to minimize the current used by frequency generators.
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate one or more enable signals in response to a first control signal and a clock signal. The second circuit may be configured to generate an output signal in response to the one or more enable signals and the clock signal. The first circuit may be configured to sample a frequency of the clock signal.
The objects, features and advantages of the present invention include providing a method and/or architecture for controlling a frequency generator that may (i) sample an external clock frequency, allowing a generator to be deselected most of the time, thereby saving current consumption (ICC); (ii) generate a sample at regular intervals; (iii) detect a power-up and suspend the sample until the board clock has locked to the correct frequency; (iv) allow a separate external reset that forces a system reset and a frequency sample; and/or (v) detect illegal internal logic states in the system and force both a reset and the frequency sample to ensure a correct frequency.